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Information on Windows Logo Kit 1.6 The Windows Logo Kit (WLK) 1.6 will ship in alignment with the release of Windows 7 Service Pack 1 (SP1). This release will enable new logo programs and enforce requirements with effective dates of December 2010. As part of this release, the Driver Test Manager (DTM) Controller will be installed on the Windows Server 2008 R2 operating system (64-bit) rather than Windows Server 2003 SP2. New and retiring logo programs will be announced in an upcoming newsletter.
New Logo Program Category: Filter Drivers The Windows Logo Program team would like inform our partners about a new logo category for filter drivers. The filter driver category is new in Windows Logo Kit (WLK) 1.6, and it is designed specifically for filter drivers operating in the Windows kernel. Common classes of these drivers are anti-virus filters. The filter category is comprised of the following requirements: - FILTER-001: A File System Filter Driver must be a Mini-Filter driver using the File Systems Filter Manager.
- FILTER-002: A Network Filter Driver must make use of the Network Windows Filtering Platform (WFP).
- FILTER-003: Kernel Mode Filter Drivers are architected to maximize reliability and functionality of Windows as well as interact accurately with the core components of the operating system.
These requirements are intended to help improve the quality of filter drivers by enforcing adherence to Windows recommended models, and detecting common driver bugs that may degrade the functionality, reliability, or performance of Windows. Note that while the filter driver category is designed for those operating in the Windows kernel, it is not limited to drivers that support hardware or those that run kernel. For more information on these requirements, see LogoPoint, which can be accessed through your Winqual account at: https://winqual.microsoft.com/.
DISPLAY-0113 Retired Immediately DISPLAY-0113, "Network Enabled Projectors display basic connection information on the startup splash screen when no input signal is detected," has been retired in response to partner feedback. This requirement inadvertently restricted projectors failing to support two simultaneous input modes; however, it is acceptable for users to select the network mode before network projection is expected to function. There are no tests in Windows Logo Kit (WLK) for this requirement, so there will be no changes to testing.
Errata Expiring Before November 1, 2010 Expiring July 13, 2010: | Errata # | Errata title | | 30 | PCIHCT: ASPM Capability Support test runs unconditionally on instead of as "Role-Based Error Reporting Capability" | | 31 | PCI Compliance test fails Advanced Error Reporting portion of the test with Assertion FB88100C-4655-42AF-87A4-857EDE0DE6D3 | | 33 | PCI Compliance fails Cardbus Controllers on Assertion 6785AA02-FC90-444C-931D-9D4B120A0ED6 | | 35 | PCI Hardware Compliance Test fails Device Capabilities register that do not always return | | 36 | PCI Hardware Compliance Test fails Device Capabilities register on Assertion 7788AEB9-8CFF-44D0-AA4F-898E05D9AE2A: FAILED | | 38 | PCI Compliance fails TYP2_IoBaseUpperHalf (68C54D92-6B38-4063-9B51-F5A4B9558147) | | 61 | PCI Compliance: TYP2_IoLimitUpperHalf (B6B64850-679D-4767-A17A-70DACA832CAD | | 69 | PCI Compliance: PWRM_PmData_DataSelect (5A75C8B5-3EBB-4836-8AF2-84A049AF808D) | | 70 | PCI Compliance: TYP1_PrimaryDiscardTimer (E06D175E-E56E-489A-96E2-02CA507EFDB9 | | 193 | PCI Compliance test fails with advisory non-fatal mask error on PCIe 1.1 devices [52942EDA-0F18-46ED-82BD-91D6AA8BDDBC | | 204 | PCI Compliance test fails Assertion: 9CB9EE90-AF3F-40EC-8278-733F6DA9F Bit 5 in the Uncorrectable Error Severity register in the AERC table must be read-only and always return 1 | | 215 | PCI Compliance test fails PCI-X devices that do not have MSI or MSI-X capability | | 220 | PCI Compliance - Test Header Log register of the Advanced Error Reporting Capability table must be read-only | | 327 | PCI Compliance - Endpoint Acceptable Latencies tested according to PCIe 1.1 and not 1.0a | | 344 | PCI Compliance - Interrupt Line register of the Header table must be read-writable | | 351 | PCI Compliance - Bit 17 (Receiver Overflow Error Severity) in the Uncorrectable Error Severity register (offset Ch) in the Advanced Error Reporting Capability table must be read-only and always return 1 |
| Errata # | Errata title | | 352 | PCI Compliance - Bit 2 (Reserved_1) in the Link Control register (offset 10h) in the PCI Express Capability table must be read-only and always return 0 | | 354 | PCI Compliance - Bit 20 (Data Link Layer Link Active Reporting Capable) in the Link Capabilities register (offset Ch) in the PCI Express Capability table must be read-only. | | 355 | PCI Compliance Message Upper Address register of the MSI Capability table must be read-writable for 64 bit address capable devices | | 356 | PCI Compliance - Bit range 11:10 (ASPM Support)in the Link Capabilities register (offset Ch) in the PCI Express Capability table must be read-only | | 385 | PCI Compliance - Header Log (1st DW) register of the Advanced Error Reporting Capability table must be read-only. Assertion: 6D047608-9AB2-4A28-AD3F-C60DFA7F4AD0 | | 395 | PCI Compliance - Class Code register of the Header table must be read-only. | | 396 | PCI Compliance - Min_Gnt register of the Header table must be read-only and always return 0. | | 403 | PCI Compliance - Bit 0 (Correctable Error Detected) in the Device Status register (offset Ah) in the PCI Express Capability table must be clearable when it is set . Assertion B76FABD4-1C61-46FF-B6D9-155FCBB551EA | | 430 | PCI Compliance - Fails Assertion FBABE47C-6E20-4F1B-B7A1-6F073D77F8B2 | | 431 | PCI Compliance - Fails Assertion D4D19854-F0B7-4952-835A-1270434648EC | | 433 | PCI Compliance - Fails Assertion 3AFC2E6D-326C-4A96-AC6B-987D4F809233 | | 452 | PCI Compliance - Bit 0 (Correctable Error Detected) in the Device Status register (offset Ah) in the PCI Express Capability table must not change value on write of 0 | | 472 | PCI Compliance - New table Virtual Channel Arbitration Table overlaps existing table Virtual Channel Capability (ID2) | | 488 | PCI Compliance - Bit 15 (PME_Status) in the Power Management Control/Status register (offset 4h) in the Power Management Capability table must default to 0 if PME# from D3 cold is not supported. | | 490 | PCI Compliance - Bit range 9:4 (Negotiated Link Width)in the Link Status register (offset 12h) in the PCI Express Capability table is 0h.Assertion CF68482E-9EEF-45B4-A8B8-1379AB6CF94A | | 490 | Bit range 9:4 (Negotiated Link Width)in the Link Status register (offset 12h) in the PCI Express Capability table is 0h.Assertion CF68482E-9EEF-45B4-A8B8-1379AB6CF94A |
| Errata # | Errata title | | 497 | PCI Compliance - Bit range 1:0 (Reserved)in the Message Address register (offset 4h) in the MSI Capability table must be read-only and always return 0. Assertion A99A9B93-292B-457B-8CB6-0855447A8DF3 | | 520 | PCI Compliance Capabilities Pointer register of the Header table must be read-only | | 521 | PCI Compliance Capabilities Pointer register of the Header table cannot have a value of 0h if the Status register indicates otherwise | | 523 | PCI Compliance Enhanced Capability Header Register of the Virtual Channel capability (ID2) | | 524 | PCI Compliance Bit range 31:28 (Reserved_2)in the Device Capabilities register (offset 4h) in the PCI Express Capability table must be read-only | | 532 | PCI Compliance - Bit range 25:18 (Captured Slot Power Limit Value)in the Device Capabilities register (offset 4h) in the PCI Express Capability table must be read-only and always return 0. | | 538 | PCI Compliance - New table Port Arbitration Table #0 overlaps existing table Virtual Channel Capability (ID2) | | 576 | PCI Compliance - A PCI-X device that generates interrupts must have an MSI or MSI-X capability. Assertion 24078F7D-D376-4557-9A43-4E4DC3AA3E63 | | 589 | PCI Compliance - Bit range 19:16 (Capability Version)in the Enhanced Capability Header register (offset 0h) in the XYZ Capability table must be read-only | | 590 | PCI Compliance - Interrupt Pin register of the Header table must be read-only. Assertion 28AAA17F-22EB-4CB5-BD9F-28FDCE48088D | | 605 | PCI Compliance - Trying to write a value=0x** that can't fit in bit range=Port Arbitration Select (bit count=3) | | 658 | Bit 8 (Slot Implemented) in the PCI Express Capabilities register (offset 2h) in the PCI Express Capability table must be read-only | | 659 | Bit 6 (Presence Detect State) in the Slot Status register (offset 1Ah) in the PCI Express Capability table must be read-only and always return 1 for switch downstream ports and root ports which do not implement a slot | | 680 | PCI Compliance - Bit 0 (Load VC Arbitration Table) in the Port VC Control register (offset Ch) in the Virtual Channel Capability (ID2) table must be read-only and always return 0 even though it is technically read-write. | | 681 | PCI Compliance - Bit 16 (Load Port Arbitration Table) in the VC Resource Control #0 register (offset 14h) in the Virtual Channel Capability (ID2) table must be read-only and always return 0 for switch ports, root ports and RCRB, even though it is technically read-write. |
| Errata # | Errata title | | 729 | PCI Compliance - Unexpected Header Type = 255 | | 739 | PCI Compliance - Bit range 14:12 (Max_Read_Request_Size)in the Device Control register (offset 8h) in the PCI Express Capability table must be read-writable if implemented. | | 755 | PCI Compliance Bit range 6:10 of the Slot Control register of the PCI Express capability is not correctly tested | | 832 | PCI Compliance - Operating mode bits of the class code register are not being tested properly | | 833 | PCI Compliance - Error Reporting Capable bits 4:0 of the Device Control Register in the PCI Express capability aren't tested correctly | | 875 | PCI Compliance - Slot Power Limit Value and Slot Power Limit Scale fields of the Slot Capabilities register shouldn't be tested | | 934 | PCI Compliance - Bit range 3:0 (Capability Version)in the PCI Express Capabilities register (offset 2h) in the PCI Express Capability table must be read-only . (Assertion B8334971-DD44-42C4-9DCB-0F58E512D0DF) | | 960 | PCI Compliance - Uncorrectable Error Mask and Severity Registers of the AERC are not being tested correctly. 3CDD17AF_FF8BC1A1_461CA4DE | | 1167 | PCIHCT - Bit range 23:21 (Reserved)in the Link Capabilities register (offset Ch) in the PCI Express Capability table must be read-only and always return 0 | | 1168 | PCIHCT - Bit range 15:9 (Reserved_2)in the Link Control register (offset 10h) in the PCI Express Capability table must be read-only and always return 0 | | 1169 | PCIHCT - Bit 11 (Electromechanical Interlock Control) in the Slot Control register (offset 18h) in the PCI Express Capability table must be read-writable . (Assertion 4976C48A-EAAE-4171-A890-16C1E5810B2D) | | 1171 | PCIHCT - Bit range 15:14 (Reserved)in the Link Status register (offset 12h) in the PCI Express Capability table must be read-only and always return 0 . (Assertion 2DF29F4E-C365-4B8D-9A72-0726AD8F53A6) | | 1180 | PCI Compliance - Data Link Layer Link Active bit is set but Link Active Reporting Capable is not. Assertion DC62767C-23C3-4668-9745-535E7B351382 | | 1221 | PCI Compliance incorrectly tests the PCIe to Cardbus bridges. (Assertion 74266472-F9F0-4021-A418-A0DBB694336B | | 1222 | PCI Compliance - Bit 5 (VGA Palette Snoop) in the Command register (offset 4h) in the Header table must be read-only and always return 0 . It was found to be read-writeable. (Assertion CF73318D-AB13-4367-A15A-ABDCEB29E116) |
| Errata # | Errata title | | 1223 | PCI Compliance - Bit range 15:0 (Extended Capability ID)in the Enhanced Capability Header register (offset 0h) in the XYZ table must be read-only. (Assertion CBC6377A-5F74-44C6-9A32-053459F2112D0) | | 1279 | Reinstall with IO doesn't consider other methods of install/uninstall | | 1594 | ERRATA: USB: USB Host Controller Enable Disable Test: Allow more time for devices to re-enumerate after re-enabling all controllers - 2 | | 1617 | USB Controller Power State Test fails due to controller reset on S4 resume |
Expiring August 1, 2010: | Errata # | Errata title | | 1806 | ERRATA: HAL Timer test fails KeStallExecutionProcessor Backoff Test case due to test problem with processor implementation | | 1811 | ERRATA: USB Descriptor test incorrectly fails when device returns 'STALL' code |
Expiring August 31, 2010: | Errata # | Errata title | | 1338 | UAA Test: PREVIEW Errata: This test enforces Low Power DCN requirement that D3 Cold support entails EPSS support |
Expiring September 30, 2010: | Errata # | Errata title | | 1198 | UAA Test Preview errata: S/PDIF pin "Pin Sense" responses cannot use "Impedance" bits |
Windows Summit 2010 Virtual Event: The Extended Device Track Launched June 30th! Windows Summit 2010 is a virtual event for software and hardware developers, designers, engineers, and testers, who build or want to build hardware and software solutions on the Windows 7 and Internet Explorer platforms. On June 30, the Device track was extended with a new set of Windows Summit 2010 technical sessions and virtual workshops. The workshops focus on Device Stage for all types of devices, and cover a new tool that simplifies implementation of Device Stage for your products. Session topics include: - Network Device Pairing
- Submitting Device Metadata Packages
- Play To
- Windows Logo Program
Device, System and Software Tracks Specialized content for the Device, System, and Software tracks is now available online. From the convenience of your computer, access tools, resources, and information about building great products on Windows 7 and Internet Explorer, including information that addresses the Windows Logo Program - from what you need to know to certify your product to what's new in the Windows Logo Kit (WLK) 1.5. To begin, simply sign in at http://www.microsoft.com/windows/windows-summit/default.aspx?ocid=sum10_lognews. Here's a sampling of the sessions currently available: - Device track, led by Mark Relph, Senior Director, Windows Developer and PC Ecosystem Team:
- The Windows Logo Program for Hardware and Devices: Getting Started
- The Windows Logo Kit: What's New in WLK 1.5
- Windows 7 Device Content and Web Resources
- Developing Your Device Experience Strategy
- System track, led by Brad Brooks, Corporate Vice President, Windows Consumer Marketing and Product Management:
- Windows 7 Imaging and Deployment Tools Overview
- Understanding the Windows Logo Program for Systems
- Building Troubleshooters
- Using the Mobile Broadband Platform in Windows 7
- Software track, led by Dean Hachamovitch, General Manager, Internet Explorer Team:
- Developing Multi-Touch Applications for Natural Experiences
- Unleashing the Latest Innovations in Modern Graphics Hardware with Windows 7
- Windows 7 Ribbon: The Next Generation User Experience for Presenting Commands in Windows Applications
- Extending Battery Life by Creating Energy-Efficient Applications
Track content is available 24x7. You can watch all the sessions or choose the ones that interest you the most. In addition to track content and the opening talks, you can view questions that were submitted to the experts along with the experts' answers. To see a full list of sessions and to learn more, visit: http://www.microsoft.com/windows/windows-summit/default.aspx?ocid=sum10_lognews.
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